View MC3368006_754706.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MC33680 Dual DC-DC Regulator for Electronic Organizer
The MC33680 is a dual DC-DC regulator designed for electronic organizer applications. Both regulators apply Pulse-Frequency-Modulation (PFM). The main step-up regulator output can be externally adjusted from 2.7V to 5V. An internal synchronous rectifier is used to ensure high efficiency (achieve 87%). The auxiliary regulator with a built-in power transistor can be configured to produce a wide range of positive voltage (can be used for LCD contrast voltage). This voltage can be adjusted from +5V to +25V by an external potentiometer. The MC33680 has been designed for battery powered hand-held products. With the low start-up voltage from 1V and the low quiescent current (typical 35 A); the MC33680 is best suited to operate from 1 to 2 AA/ AAA cell. Moreover, supervisory functions such as low battery detection, CPU Power-Good signal, and back-up battery control, for lithium battery or supercap are also included in the chip.
FEATURES: http://onsemi.com
32
1
32-LEAD LQFP FTB SUFFIX CASE 873A
PIN CONNECTIONS & DEVICE MARKING
NC VAUXBASE VAUXCHG VAUXBDV VAUXFBN NC VAUXFBP VAUXEN VAUXSW VAUXEMR LIBATIN LIBATOUT NC VMAINGND VMAINSW VMAIN MC33680 FTB AWLYYWW NC DGND LIBATCL LIBATON LOWBATB PORB DGND LOWBATSEN
* Low Input Voltage, 1V up * Low Quiescent Current in Standby Mode: 35A typical * PFM and Synchronous Rectification to ensure high efficiency
(87% @60mA Load)
* Adjustable Main Output: +2.7V to +5V * * * * * *
nominal 3.3V @ 100mA max, with 1.8V input Auxiliary Output Voltage: +5V to +25V +5V @ 25mA max, with 1.8V input +25V @ 15mA max, with 1.8V input Current Limit Protection Power-Good Signal with Programmable Delay Battery Low Detection Lithium Battery or Supercap Back-up 32-Pin LQFP Package
APPLICATIONS:
* Digital Organizer and Dictionary * Dual Output Power Supply (For MPU, Logic, Memory, LCD) * Handheld Battery Powered Device (1-2 AA/AAA cell)
ORDERING INFORMATION
Device MC33680FTB MC33680FTBR2 Package LQFP LQFP Shipping 1250 Tray / Drypack 1800 / Tape & Reel
(c) Semiconductor Components Industries, LLC, 2006
July, 2006 - Rev. 4
1
VMAINFB VBAT VBAT VDD PDELAY VREF AGND IREF
(Top View)
Publication Order Number: MC33680/D
MC33680
VBAT CMAINb 100 pF RMAINb 4 VDD 3 5 VBAT 2 VBAT 1 VMAINFB 1000 kW L1 33 mH MBRA130LT1
VBAT RIref 480 kW 8 VBAT 300 kW RLBa LOBAT- SEN 9 900 kW RLBb DGND 10 PORB 11 Power-On Reset S Qb DGND +ve Edge Delay for Max. ON Time R Q M1 IREF 7 AGND 6 CPOR 80 nF VREF + CVDD 20 mF 5 PDELAY +
ZLC
COMP3
31 VMAINSW 32 VMAIN
VDD
senseFET
M2 CMAIN 100 mF
+
VMAINGND 30
1-SHOT x2 for Min. OFF Time R S Q ILIM COMP2 Voltage Reference 1.22 V COMP1 VCOMP AGND Main Regulator with Synchronous Rectifier 0.5 V +ve Edge Delay LOWBATB 12 LIBATON 13 LIBATCL 14 DGND 15 Voltage Reference Current Bias & Supervisory 17 VAUXEN 18 VAUXFBP 20 VAUXFBN 200 kW RAUXa Lithium Battery Backup AGND 0.85 V, 1.1 V VCOMP COMP1 S 1-SHOT for Min. OFF Time AGND Auxiliary Regulator 2200 kW RAUXb 21 VAUXBDV VBAT Qb for Max. ON Time R Q Q1
VDD
LIBATOUT 28 LIBATIN
DGND
27 VBAT L2 33 mH MBRA140T3 25 VAUXSW
senseBJT
CAUX 30 mF
+
VAUXEMR ILIM COMP2 26
22 VAUXCHG
23 VAUXBASE
Figure 1. Detailed Application Block Diagram
http://onsemi.com
2
MC33680
TIMING DIAGRAMS
VBAT VMAINreg - 0.15 V VMAINreg
VMAIN
T
POR
+ 1.22 0.5
C por
RIref
PORB
tPORC
VAUXEN
Figure 2. Startup Timing
VBAT
LOWBAT Threshold
LOWBATB
VMAIN VMAINreg - 0.5 V
PORB
Figure 3. Power Down Timing
http://onsemi.com
3
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A AAAAAAAAA AAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A
Pin No. 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 10 11 9 8 7 6 5 4 3 2 1
LOWBATSEN VMAINGND VAUXBASE VAUXCHG VAUXEMR LOWBATB LIBATOUT VMAINSW
Function
VAUXBDV
VAUXFBN
VAUXFBP
VMAINFB
VAUXSW
LIBATON
VAUXEN
LIBATCL
PDELAY
LIBATIN
VMAIN
DGND
DGND
AGND
PORB
VREF
VBAT
VBAT
IREF
VDD
NC
NC
NC
NC
Type/Direction
Analog / Output
Analog / Output
Analog / Output
Analog / Output
Analog / Output
Analog / Output
Analog / Output
Analog / Output
CMOS / Output
CMOS / Output
Analog Ground
Power Ground
Digital Ground
Digital Ground
Analog / Input
Analog / Input
Analog / Input
Analog / Input
Analog / Input
Analog / Input
Analog / Input
Analog / Input
CMOS / Input
CMOS / Input
CMOS / Input
Power
Power
Power
PIN FUNCTION DESCRIPTION
http://onsemi.com
VMAIN output VMAIN inductor connection Ground for VMAIN low side switch no connection Lithium battery output Lithium battery input for backup purposes Emitter output of the VAUX power BJT Collector output of the VAUX power BJT no connection test pin test pin VAUX BJT base drive circuit power supply Feedback pin for VAUX no connection Feedback pin for VAUX VAUX enable, Active high no connection microprocessor control signal for Lithium battery backup switch, if it is HIGH, the switch is controlled by LIBATON, otherwise, controlled by internal logic microprocessor control signal for Lithium battery backup switch, the switch is ON when LIBATON=HIGH and LIBATCL=HIGH Active LOW low battery detect output Active LOW Power-On reset signal Resistive network connection for defining low battery detect threshold Resistor connection for defining internal current bias and PDELAY current Bandgap Reference output voltage. Nominal voltage is 1.25V Capacitor connection for defining Power-On signal delay Connect to decoupling capacitor for internal logic supply Main battery supply Main battery supply Feedback pin for VMAIN
MC33680
4
Description
MC33680
ABSOLUTE MAXIMUM RATINGS (TA = 25C, unless otherwise noted.)
Parameter Power Supply Voltage Digital Pin Voltage General Analog Pin Voltage Pin VAUXSW to Pin VAUXEMR Voltage (Continuous) Pin VMAINSW to Pin VMAIN Voltage (Continuous) Operating Junction Temperature Ambient Operating Temperature Storage Temperature Symbol VBAT Vdigital Vanalog VAUXCE Vsyn Ta Tj (max) Tstg Min -0.3 -0.3 -0.3 -0.3 Max 7.0 7.0 7.0 30 0.3 Unit Vdc Vdc Vdc Vdc Vdc C C C
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A A A A A A A A A AAAAAAAAAAAAAAA A A A AAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A A A A A A A A A AAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A
150 70 0 -50 150 otherwise noted.)
STATIC ELECTRICAL CHARACTERISTICS (Circuit of Figure 1, VP = 1.8V, Iload = 0 mA, TA = 0 to 70C unless
Rating Symbol VBAT Vmain Vmain_range I3.3_1.8 frequency4 Freqmax_VM ILIM_VM VAUX_range Freqmax_VL ILIM_VL Iqstandby Vrefno_load threshold6 VLOBAT_L VLOBAT_H IchgPDELAY VthPDELAY 1.16 0.8 1.05 0.8 1.16 1.0 35 1.22 0.85 1.1 1.0 1.22 0.85 5.0 1.0 Min 1.0 3.1 2.7 3.3 Typ
Max
Unit V
Operating Supply
Voltage1
VMAIN output voltage VMAIN output voltage range2 VMAIN output current3 VMAIN maximum switching
3.5 5.0 200 100 1.15 25 120
V V mA kHz A V kHz A
VMAIN peak coil static current limit VAUX output voltage range VAUX maximum switching frequency VAUX peak coil static current limit Quiescent Supply Current at Standby Mode5 Reference Voltage @ no load Battery Low Detect lower hysteresis
60 1.28 0.9 1.15 1.2 1.28
A V V V A V
Battery Low Detect upper hysteresis threshold PDELAY Pin output charging current PDELAY Pin voltage threshold
NOTE: 1. Output current capability is reduced with supply voltage due to decreased energy transfer. The supply voltage must not be higher than VMAIN+0.6V to ensure boost operation. Max Start-up loading is typically 1V at 400 A, 1.8V at 4.4 mA, and 2.2V at 88 mA. NOTE: 2. Output voltage can be adjusted by external resistor to the VMAINFB pin. NOTE: 3. At VBAT = 1.8V, output current capability increases with VBAT. NOTE: 4. Only when current limit is not reached. NOTE: 5. This is average current consumed by the IC from VDD, which is low-pass filtered from VMAIN, when only VMAIN is enabled and at no loading. NOTE: 6. This is the minimum of "LOWBATB" threshold for battery voltage, the threshold can be increased by external resistor divider from "VBAT" to "LOWBATSEN".
http://onsemi.com
5
MC33680
DYNAMIC ELECTRICAL CHARACTERISTICS (Refer to TIMING DIAGRAMS, TA = 0 to 70C unless otherwise noted.)
Rating Minimum PORB to Control delay Symbol tPORC Min Typ Max 500 Unit nS
90% Eff VMAIN , EFFICIENCY OF VMAIN (%) Eff VMAIN , EFFICIENCY OF VMAIN (%)
90%
85%
85%
80% Vin = 3V Vin = 1.8V Vin = 1.5V Vin = 1V 0 10 20 30 40 50 60 70 80 90 100
80% Iout = 10mA Iout = 60mA Iout = 100mA
75%
75%
70% IOUT_MAIN, MAIN OUTPUT CURRENT (mA)
70% 1 1.5 2 VIN, INPUT VOLTAGE (V) 2.5 3
Figure 4. Efficiency of VMAIN versus Output Current (VMAIN = 3.3 V, L = 33 uH, Various VIN)
Figure 5. Efficiency of VMAIN versus Input Voltage (VMAIN = 3.3 V, L1 = 33 uH, Various IOUT)
80% Eff VAUX , EFFICIENCY OF VAUX (%) Eff VAUX , EFFICIENCY OF VAUX (%) 75% 70% 65% 60% 55% 50% 1 3 5 7 9 11 13 15 IOUT_AUX, AUX OUTPUT CURRENT (mA) Vin = 3V Vin = 1.8V Vin = 1.5V Vin = 1V
80% 75% 70% 65% 60% 55% 50% 1 1.5 2 VIN, INPUT VOLTAGE (V) 2.5 3 Iout = 1mA Iout = 5mA Iout = 10mA Iout = 15mA
Figure 6. Efficiency of VAUX versus Output Current (VAUX = 25 V, L2 = 33 uH, Various VIN)
Figure 7. Efficiency of VAUX versus Input Voltage (VAUX = 25 V, L2 = 33 uH, Various IOUT)
http://onsemi.com
6
MC33680
80% Eff VAUX, EFFICIENCY OF VAUX (%) 75% 70% 65% 60% 55% 50% 1 3 5 7 9 11 13 15 IOUT_AUX, AUX OUTPUT CURRENT (mA) Vin = 3V Vin = 1.8V Vin = 1.5V Vin = 1V Eff VAUX, EFFICIENCY OF VAUX (%) 80% 75% 70% 65% 60% 55% 50% 1 1.5 2 VIN, INPUT VOLTAGE (V) 2.5 3 Iout = 1mA Iout = 5mA Iout = 10mA Iout = 15mA
Figure 8. Efficiency of VAUX versus Output Current (VAUX = 20 V, L2 = 33 uH, Various VIN)
Figure 9. Efficiency of VAUX versus Input Voltage (VAUX = 20 V, L2 = 33 uH, Various IOUT)
85% Eff VAUX, EFFICIENCY OF VAUX (%) 80% 75% 70% 65% 60% 55% 50% 45% 40% 1 5 10 15 20 Vin = 3V Vin = 2.4V Vin = 1.8V Vin = 1.5V Vin = 1V 25 30 35 Eff VAUX, EFFICIENCY OF VAUX (%)
85% 80% 75% 70% 65% 50% 1 1.5 2 VIN, INPUT VOLTAGE (V) 2.5 3 IOUT_AUX, AUX OUTPUT CURRENT (mA) Iout = 1V Iout = 5V Iout = 10V Iout = 15V Iout = 25V
Figure 10. Efficiency of VAUX versus Output Current (VAUX = 5 V, L2 = 82 uH, Various VIN)
Figure 11. Efficiency of VAUX versus Input Voltage (VAUX = 5 V, L2 = 82 uH, Various IOUT)
http://onsemi.com
7
MC33680
20 uS / div 1: VMAIN = 3.3 V (50 mV/div, AC COUPLED) 2: Voltage at VMAINSW (1 V/div)
10 uS / div 1: VMAIN = 3.3 V (50 mV/div, AC COUPLED) 2: Voltage at VMAINSW (1 V/div)
Figure 12. VMAIN Output Ripple (Medium Load)
Figure 13. VMAIN Output Ripple (Heavy Load)
20 uS / div 1: VAUX = 20 V (50 mV/div, AC COUPLED) 2: Voltage at VAUXSW (10 V/div)
10 uS / div 1: VAUX = 20 V (50 mV/div, AC COUPLED) 2: Voltage at VAUXSW (10 V/div)
Figure 14. VAUX Output Ripple (Medium Load)
Figure 15. VAUX Output Ripple (Heavy Load)
50 mS / div 1: VMAIN from 1 V to 3.3 V (1 V/div) 2: Voltage of PORB (2 V/div) 3: Voltage of ENABLE (2 V/div)
5 mS / div 1: VAUX from 1.8 V to 20 V (5 V/div) 2: VAUXEN (2 V/div)
Figure 16. VMAIN Startup and Power-Good Signal
Figure 17. VAUX Startup
http://onsemi.com
8
MC33680
DETAILED OPERATING DESCRIPTION
General Iref + 0.5 (A) RIref
The MC33680 is a dual DC-DC regulator designed for electronic organizer applications. Both regulators apply Pulse-Frequency-Modulation (PFM). The main boost regulator output can be externally adjusted from 2.7V to 5V. An internal synchronous rectifier is used to ensure high efficiency (achieve 87%). The auxiliary regulator with a built-in power transistor can be configured to produce a wide range of positive voltage (can be used for LCD contrast voltage). This voltage can be adjusted from +5V to +25V by an external potentiometer. The MC33680 has been designed for battery powered hand-held products. With the low start-up voltage from 1V and the low quiescent current (typical 35 A), the MC33680 is best suited to operate from 1 to 2 AA/ AAA cell. Moreover, supervisory functions such as low battery detection, CPU Power-Good signal, and back-up battery control, are also included in the chip. It makes the MC33680 the best one-chip power management solution for applications such as electronic organizers and PDAs.
Pulse Frequency Modulation (PFM)
This bias current is used for all internal current bias as well as setting VMAIN value. For the latter application, Iref is doubled and fed as current sink at Pin 1. With external resistor RMAINb tied from Pin1 to Pin32, a constant voltage level shift is generated in between the two pins. In close-loop operation, voltage at Pin 1 (i.e. Output feedback voltage) is needed to be regulated at the internal reference voltage level, 1.22V. Therefore, the delta voltage across Pin 1 and Pin 32 which can be adjusted by RMAINb determines the Main Output voltage. If the feedback voltage drops below 1.22V, internal comparator sets switching cycle to start. So, VMAIN can be calculated as follows.
VMAIN + 1.22 ) RMAINb (V) RIref
Both regulators apply PFM. With this switching scheme, every cycle is started as the feedback voltage is lower than the internal reference. This is normally performed by internal comparator. As cycle starts, Low-Side switch (i.e. M1 in Figure 1) is turned ON for a fixed ON time duration (namely, Ton) unless current limit comparator senses coil current has reached its preset limit. In the latter case, M1 is OFF instantly. So Ton is defined as the maximum ON time of M1. When M1 is ON, coil current ramps up, so energy is being stored inside the coil. At the moment just after M1 is OFF, the Synchronous Rectifier (i.e. M2 in Figure 1) or any rectification device (such as Schottky Diode of Auxiliary Regulator) is turned ON to direct coil current to charge up the output bulk capacitor. Provided that coil current limit is not reached, every switching cycle delivers fixed amount of energy to the bulk capacitor. For higher loading, a larger amount of energy (Charge) is withdrawn from the bulk capacitor, and a larger amount of Charge is then supplied to the bulk capacitor to regulate output voltage. This implies switching frequency is increased; and vice-versa.
Main Regulator
From the above equation, although VMAIN can be adjusted by RMAINb and RIref ratio, for setting VMAIN, it is suggested, by changing RMAINb value with RIref kept at 480K. Since changing RIref will alter internal bias current which will affect timing functions of Max ON time (TON1 ) and Min OFF time (TOFF1 ). Their relationships are as follows;
T + 1.7 ON 1 T + 6.4 OFF 1 10 -11 10 -12 RIref (S) RIref (S)
Continuous Conduction Mode and Discontinuous Conduction Mode
Figure 18 shows the simplified block diagram of Main Regulator. Notice that precise bias current Iref is generated by a VI converter and external resistor RIref, where
In Figure 19, regulator is operating at Continuous Conduction Mode. A switching cycle is started as the output feedback voltage drops below internal voltage reference VREF. At that instant, the coil current is not yet zero, and it starts to ramp up for the next cycle. As the coil current ramps up, loading makes the output voltage to decrease as the energy supply path to the output bulk capacitor is disconnected. After Ton elapses, M1 is OFF, M2 is ON, energy is pumped to the bulk capacitor. Output voltage is increased as excessive charge is pumped in, then it is decreased after the coil current drops below the loading. Notice the abrupt spike of output voltage is due to ESR of the bulk capacitor. Feedback voltage can be resistor-divided down or level-shift down from the output voltage. As this feedback voltage drops below VREF, next switching cycle starts.
http://onsemi.com
9
MC33680
DETAILED OPERATING DESCRIPTION (Cont'd)
VBAT CMAINb 100 pF 2 x Iref RMAINb 1000 kOhm 31 ZLC COMP3 x2 0.5 V Iref IREF 8 RIref 480 kOhm Voltage Reference 1.22 V VCOMP COMP1 VDD 1-SHOT for Min. OFF Time R S AGND Voltage Reference & Current Bias Main Regulator with Synchronous Rectifier Q ILIM DGND COMP2 S Qb DGND VMAINGND 30 R Q M1 +ve Edge Delay for Max. ON Time VDD senseFET M2 VMAIN 32 CMAIN 100 uF + VMAINSW L1 33uH
1
VMAINFB
AGND
Figure 18. Simplified Block Diagram of Main Regulator
In Figure 20, regulator is operating at Discontinuous Conduction Mode, waveforms are similar to those of Figure 19. However, coil current drops to zero before next switching cycle starts. To estimate conduction mode, below equation can be used.
Iroom + h TON 2L Vin 2 *I LOAD Vout
T + SW
T ON 1 * h Vin Vout I LOAD T ON T SW )
(S); Vin 2 T ON (A) L
I+ pk
1*
where, is efficiency, refer to Figure 4
For Discontinuous Conduction mode, provided that current limit is not reached,
T + SW 2 Vin @ T ON 2@L@I LOAD @ Vout * 1 h@Vin (S);
if Iroom > 0, the regulator is at Discontinuous Conduction mode if Iroom = 0, the regulator is at Critical Conduction mode where coil current just drops to zero and next cycle starts. if Iroom < 0, the regulator is at Continuous Conduction mode For Continuous Conduction mode, provided that current limit is not reached,
I + Vin @ T (A) pk ON L
http://onsemi.com
10
MC33680
Cycle Starts VREF Feedback Voltage tdl M1 ON tdh M2 OFF Ipk M2 ON M2 OFF TON M2 ON M2 OFF M2 ON M1 OFF M1 ON M1 OFF M1 ON M1 OFF
Loading Current, ILOAD Coil Current VMAIN + 1 V VMAIN TSW
V@SW
0V
VMAIN Zoom-In
Figure 19. Waveforms of Continuous Conduction Mode
Cycle Starts Feedback Voltage VREF tdl M1 ON tdh M2 OFF M2 OFF M2 OFF M1 OFF M1 ON M1 OFF M1 ON M1 OFF
Ipk
TON
Loading Current, ILOAD Coil Current VMAIN + 1 V VMAIN VIN V@SW VMAIN Zoom-In 0V TSW
Figure 20. Waveforms of Discontinuous Conduction Mode http://onsemi.com
11
MC33680
DETAILED OPERATING DESCRIPTION (Cont'd)
Synchronous Rectification
Therefore, determination on the offset voltage is essential for optimum performance.
Auxiliary Regulator
A Synchronous Rectifier is used in the main regulator to enhance efficiency. Synchronous rectifier is normally realized by powerFET with gate control circuitry which, however, involved relative complicated timing concerns. In Figure 19, as main switch M1 is being turned OFF, if the synchronous switch M2 is just turned ON with M1 not being completely turned OFF, current will be shunted from the output bulk capacitor through M2 and M1 to ground. This power loss lowers overall efficiency. So a certain amount of dead time is introduced to make sure M1 is completely OFF before M2 is being turned ON, this timing is indicated as tdh in Figure 20. When the main regulator is operating in continuous mode, as M2 is being turned OFF, and M1 is just turned ON with M2 not being completed OFF, the above mentioned situation will occur. So dead time is introduced to make sure M2 is completed OFF before M1 is being turned ON, this is indicated as tdl in Figure 20. When the main regulator is operating in discontinuous mode, as coil current is dropped to zero, M2 is supposed to be OFF. Fail to do so, reverse current will flow from the output bulk capacitor through M2 and then the inductor to the battery input. It causes damage to the battery. So M2-voltage-drop sensing comparator (COMP3 of Figure 18) comes with fixed offset voltage to switch M2 OFF before any reverse current builds up. However, if M2 is switch OFF too early, large residue coil current flows through the body diode of M2 and increases conduction loss.
The Auxiliary Regulator is a boost regulator, applies PFM scheme to enhance high efficiency and reduce quiescent current. An internal voltage comparator (COMP1 of Figure 21) detects when the voltage of Pin VAUXFBN drops below that of Pin VAUXFBP. The internal power BJT is then switched ON for a fixed-ON-time (or until the internal current limit is reached), and coil current is allowed to build up. As the BJT is switched OFF, coil current will flow through the external Schottky diode to charge up the bulk capacitor. After a fixed-mimimum-OFF time elapses, next switching cycle will start if the output of the voltage comparator is HIGH. Refer to Figure 21, the VAUX regulation level is determined by the equation as follows,
R V + VAUXFBP @ 1 ) AUXb AUX R AUXa (V)
Where Max ON Time, TON2, and Min OFF Time, TOFF2 can be determined by the following equations.
T + 1.7 10 -11 RIref (S) ON 2 T + 2.1 10 -12 RIref (S) OFF 2
As the Auxiliary Regulator control scheme is the same as the Main Regulator, equations for conduction mode, Tsw and Ipk can also be applied, However, h to be used for calculation is referred to Figures 6, 8, or 10.
VBAT L2 33uH
RAUXa 200 kOhm VREF
RAUXb 2200 kOhm VBAT
VAUXFBP 18
VAUXFBN 20 +ve Edge Delay
VAUXBDV 21
VAUXSW 25 senseBJT + CAUX 33 uF Q1 VAUXEMR
for Max. ON Time R Q
VCOMP COMP1
S
Qb
26
1-SHOT for Min. OFF Time ILIM COMP2 Auxiliary Regulator
AGND
Figure 21. Simplified Block Diagram of Auxiliary Regulator
http://onsemi.com
12
MC33680
DETAILED OPERATING DESCRIPTION (Cont'd)
Current Limit for Both regulators V + 1.1 LOBAThigh R 1 ) LBa R LBb R 1 ) LBa R LBb (V)
From Figure 18 and Figure 21, sense devices (senseFET or senseBJT) are applied to sample coil current as the low-side switch is ON. With that sample current flowing through a sense resistor, sense-voltage is developed. Threshold detector (COMP2 in both Figures) detects whether the sense-voltage is higher than preset level. If it happens, detector output reset the flip-flop to switch OFF low-side switch, and the switch can only be ON as next cycle starts.
Power-Good Signal
V + 0.85 LOBATlow Lithium-Battery backup
(V)
During the startup period (see Figure 2), the internal startup circuitry is enabled to pump up VMAIN to a certain voltage level, which is the user-defined VMAIN output level minus an offset of 0.15V. The internal Power-Good signal is then enabled to activate the main regulator and conditionally the auxiliary regulator. Meanwhile, the startup circuitry will be shut down. The Power-Good signal block also starts to charge up the external capacitor tied from Pin PDELAY to ground with precise constant current. As the Pin PDELAY's voltage reaches an internal set threshold, Pin PORB will go HIGH to awake the microprocessor. This delay is stated as follows;
T + 1.22 POR 0.5 C por RIref (S)
The backup conduction path which is provided by an internal power switch (typ. 13 Ohm) can be controlled by internal logic or microprocessor. If LIBATCL is LOW, the switch, which is then controlled by internal logic, is ON when the battery is removed and VMAIN is dropped below LIBATIN by more than 100mV, and returns OFF when the battery is plugged back in. If LIBATCL is HIGH, the switch is controlled by microprocessor through LIBATON. The truth table is shown in Figure 22.
Efficiency and Output Ripple
From Figure 3, if, by any chance, VMAIN is dropped below the user-defined VMAIN output level minus 0.5V, PORB will go LOW to indicate the OUTPUT LOW situation. And, the IC will continue to function until the VMAIN is dropped below 2V.
Low-Battery-Detect
For both regulators, when large values are used for feedback resistors (> 50kOhm), stray capacitance of pin 1 (VMAINFB) and pin 20 (VAUXFBN) can add "lag" to the feedback response, destabilizing the regulator and creating a larger ripple at the output. From Figure 1, ripple of Main and AUX regulator can be reduced by capacitors in parallel with RMAINb, RAUXa and RAUXb ranging from 100pF to 100nF respectively. Reducing the ripple is also with improving efficiency, system designers are recommended to do experiments on capacitance values based on the PCB design.
Bypass Capacitors
The Low-Battery-Detect block is actually a voltage comparator. Pin LOWBAT is LOW, if the voltage of external Pin LOWBATSEN is lower than 0.85V. The IC will neglect this warning signal. Pin LOWBAT will become HIGH, if the voltage of external Pin LOWBATSEN is recovered to more than 1.1V. From Figure 1, with external resistors RLBa and RLBb, thresholds of Low-Battery-Detect can be adjusted based on the equations below.
LIBATCL
0
If the metal lead from battery to coils are long, its stray resistance can put additional power loss to the system as AC current is being conducted. In that case, bypass capacitors should be placed closely to the coil, and connected from VBAT to ground. This reduces AC component of coil current passing through the long metal lead, thus minimizing that portion of power loss.
LIBATON
X
Action
The switch is ON when the battery is removed and VMAIN is dropped below LIBATIN by more than 100mV; The switch is OFF when the battery is plugged in. The switch is OFF The switch is ON
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAA AAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA
1 1 0 1
Figure 22. Lithium Battery Backup Control Truth Table
http://onsemi.com
13
MC33680
PACKAGE DIMENSIONS
32-LEAD LQFP PLASTIC PACKAGE CASE 873A-02 ISSUE A
32
A1
A
25
4X
0.20 (0.008) AB T-U Z
BASE METAL
1
B1
8
DETAIL Y
17
V1
J
9
9
-Z- S G
4X
SECTION AE-AE 0.20 (0.008) AC T-U Z
S1
DETAIL AD
-T-, -U-, -Z-
0.20 (0.008)
B
V
F
-AB-
SEATING PLANE
-AC- 0.10 (0.004) AC AE
8X
M_
R
P AE
CE
DETAIL Y
DETAIL AD
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
GAUGE PLANE
X
0.250 (0.010)
H
W
K
Q_
http://onsemi.com
14
EE EE EE
-T-
-U-
N D
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
M
AC T-U Z
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
MC33680/D

▲Up To Search▲

Price & Availability of MC3368006

	To Download MC3368006 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .